1. Technical Field
The present invention relates generally to integrated circuit and package modeling using a simplified equivalent model generated from an intermediate model having simulation windows containing I/Os represented by current sources.
2. Related Art
Integrated circuits (ICs) and packages have become increasingly more complex as clock speeds have exceeded the gigahertz milestone. As a result, it has become increasingly important for IC designers to investigate the performance of designs prior to actual fabrication. A common mechanism to complete this investigation is to simulate input/outputs (I/Os) with modeling to determine the high speed effects on signal integrity, power supply, collapse, noise, etc. Modeling may be completed, for example, using conventional modeling software such as SPICE available from a variety of electronic design automation (EDA) vendors such as Synopsis. Conventional modeling software allows simulation of node switching of the circuits/signals and calculates results such as node voltage, waveform, etc. Ideally, a thorough investigation of design performance would be expected to simulate the entire IC and package. However, simulating an entire IC and package or even a large area thereof, is impracticable due to the large number of circuit elements used on the new ICs. In particular, setting up conventional modeling software requires input of all relevant circuit structure, which can take weeks. In addition, setting up computer resources for such a simulation can take weeks to complete, and the actual simulation can take days to complete.
One common solution to this problem is to simulate only a small core area of the IC and package and assume the core area is repeated uniformly throughout the IC design. This approach can be inaccurate because of the non-uniformity of I/O placement, or the distance between aggressive circuits, e.g., those with a high current change rate, and sensitive circuits that are susceptible to noise. Any simulation of a complex IC completed using this technique, therefore, is automatically suspect.
In view of the foregoing, there is a need in the art for a way to model a small core area that reflects complex IC floor planning and package design that is applicable where I/O placement is non-uniform.